A faster way to optimize the placements of components on a digital chip earned notice for a graduate student of electrical and computer engineering.

Mohit Sharma’s poster presentation “Design Space Exploration in the Physical Design of an AI Processor at 12 nm using Relative Placement Methodology” was named the best student paper in the category Digital, Communications and Signal Processing Circuits at the IEEE International Midwest Symposium on Circuits and Systems in Arizona in August 2023.

Sharma proposed using Relative Placement Methodology to reduce the manual effort required to place macro cells on an artificial intelligence processor, making design space exploration iterations faster. The method is based on the idea that a rectangular object can be placed in 16 different locations around another rectangular object based on its length and width.

He found that it led to a 40 per cent increase in utilization and almost 30 per cent decrease in total power requirements.

Sharma has completed his master’s degree under the guidance of professor Mohammed Khalid and is currently working for an automotive embedded systems design company in Windsor.

“I am delighted that Mohit’s work has been recognized at one of the oldest and most respected IEEE conferences in circuits and systems,” says Dr. Khalid. “Students from all over the world had applied for this award.”

He notes that Sharma’s research was part of a MITACS- and industry-funded project that dealt with the design of a power efficient AI processor: “Mohit’s innovative ideas led to significant reductions in design cost and time for this state-of-the-art AI processor.”